Building a telescope capable of spotting an Earth-like planet orbiting another star isn’t just an optical challenge. It’s a computing one.
Future observatories will need to process enormous amounts of data in real time as they continuously correct tiny distortions in their mirrors and optics. Every calculation has to happen almost instantly. Yet for many of these tasks, the biggest limitation isn’t processing power. It’s the time and energy spent moving data between memory and the processor.
Researchers at the University of Michigan believe they’ve found a better way. Their study, which will be presented at the IEEE Space Computing Conference, proposes a new generation of memory-centric computer chips designed specifically for future space telescopes, including NASA’s proposed Habitable Worlds Observatory. Rather than relying on conventional processor architectures, the team redesigned the hardware around the way the telescope actually handles data.
Traditional processors repeatedly move information back and forth between memory and the computing cores carrying out the calculations. For workloads involving huge matrix operations – exactly the kind needed to process telescope images – that constant movement becomes the real bottleneck. The processor spends as much time waiting for data as it does performing calculations.
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Instead of trying to build a faster processor, the researchers focused on reducing the amount of data that has to travel.
The team developed two alternative chip architectures. One combines stacks of high-bandwidth memory with a custom processor to move much larger volumes of information at once. The second takes a more radical approach, distributing both memory and processing across dozens of smaller SRAM chiplets so that calculations happen much closer to where the data is stored.
Keeping the processing and memory together dramatically reduces the amount of data shuttling backwards and forwards across the chip, cutting both power consumption and processing delays.
To test the designs, the researchers simulated how the chips would perform while processing data from a future space telescope. They also carried out 10,000 fault-injection simulations, introducing the kinds of errors caused by cosmic radiation to ensure the architecture could continue operating reliably in space.
The SRAM-based design produced the strongest results. Compared with an equivalent GPU-based system requiring around 3,000 watts, the proposed architecture reduced power consumption to 90 watts. By introducing an additional mathematical optimisation, that figure fell again to just 51 watts – around 59 times lower than the conventional approach.
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In space, those savings extend well beyond electricity. Every watt consumed by onboard electronics requires larger solar panels, bigger batteries and more cooling equipment. Using established spacecraft design models, the researchers estimate the lower-power architecture could reduce the mass of a future telescope from around 1,100 kg to 193 kg, potentially saving around US$430 million over a 25-year mission.
The team now plans to manufacture the SRAM chiplets and begin laboratory testing. While the research was developed with space telescopes in mind, it reflects a much broader trend in computing. Rather than building ever faster processors, engineers are increasingly redesigning hardware around specific workloads, bringing memory and computation closer together to overcome one of modern computing’s biggest hidden limitations: moving data.